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MITSUBISHI Analog ICs
M65533FP
3ch 8-bit 80MHz A/D Converters General Description The M65533FP is a CMOS 3ch 8-bit 80MHz analog-to-digital converter by sub-ranging architecture for high speed video processing. It can be realized 80MHz operation by using 2 ADCs in parallel. And it has PLL circuit generate a stable clock locked to sync signal. It is a type of "AC" connection with internal clamp circuit and variable input range. Features * 3ch 8-bit high speed A-D converters * Maximum conversion rate * Analog input Level * Digital input * Digital output * Low power dissipation * Package * Small input capacitance * Built-in Reference Voltag * Built-in Clamp circuit Applications * LCD monitor * High speed video processing Recommended Operating Condition * Supply voltage range (typ.=3.3V) 3.15 to 3.45 V * Supply voltage range (typ.=5.0V) 4.75 to 5.25 V
80 MSPS(min.) 1.0V(Typ) : 0.5 -1.5 V TTL compatible [ Vinth=1.4V ] VoH=0.7XVcc , VoL=0.3XVcc [ Io=4mA ] 700mW [ CL=10pF ] 80 pin QFP package, 0.80mm lead pitch [ PKG size(without lead) =14mm x 20mm ] 10 pF Vref(+)=1.5V+150/-330mV(*) Vref(-)=0.5V Vclamp=0.5V+/-250mV(*)
(*)Controllable by IIC BUS
for 5V I/F only
Pin configuration(Top View)
64 63 62 61 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Shown on next page
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M65533FP #XXXXXX
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Ver 3.0
'99- 5- 31
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MITSUBISHI Analog ICs
M65533FP
3ch 8-bit 80MHz A/D Converters
Pin Configuration
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 DoB5 DoB6 DoB7 DVDDB(OUT) DGNDB(OUT) DoG0 DoG1 DoG2 DoG3 DoG4 DoG5 DoG6 DoG7 DVDDG(OUT) DGNDG(OUT) DoR0 DoR1 DoR2 DoR3 DoR4 DoR5 DoR6 DoR7 DVDDR(OUT) 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BNB BVRT BVRM AVDDB AGNDB NC BCIN BVRB GNB GVRT GVRM AVDDG AGNDG NC GCIN GVRB RNB RVRT RVRM AVDDR AGNDR NC RCIN RVRB
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MITSUBISHI Analog ICs
M65533FP
3ch 8-bit 80MHz A/D Converters
Block Diagram
CP-IN AVDDR DVDDR(A/D)
1st ADC ( R signal )
Comparators(1) DVDDR(out)
RC IN RVRT RVRM RVRB RNB AGNDR DGNDR (A/D)
Ladder Resistors
SW
MUX & DeMU X
Delay & Error Correctio n
DGNDR(out) DoR0 DoR1 DoR2 DoR3 DoR4
Comparators(2)
Comparators(1) MUX & DeMU X Delay & Error Correcti on
DoR5 DoR6 DoR7
Ladder Resistors
SW
Timing Gen.
Comparators(2)
2nd ADC ( G signal )
3rd ADC ( B signal )
fFBin FH-IN fH
fCLK
PLL
SW
CLK-OUT FILTER Test1-3
EXT-CLK IN
IIC BUS
DLY-HDout
VDD(PLL) DVDD(LO) GND(PLL) DGND(LO)
DVDD(I/O 5) DGND(I/O 5)
SDA
SCL
RESET
(note) Pins for ADC is described for only R signal
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MITSUBISHI Analog ICs
M65533FP
3ch 8-bit 80MHz A/D Converters
Absolute Maximum Ratings (Ta = 25C, unless otherwise noted.)
Symbol
DVdd AVdd Vdd((I/O) VID IOUT Pd Topr Tstg
Parameter
Digital Supply Voltage Analog Supply Voltage I/O Supply Voltage Digital Input Voltage Analog Output Current Power Dissipation Operating Temperature Storage Temperature
Condition
Ratings
0 to 4.0 0 to 4.0 0 to 6.0 0 to 4.0 -30 to 0 1600 0 to +70 -40 to +150
Unit V V V V mA mW C C
In current measurement, (+) and (-) is corresponding to an inflow and an outflow current, respectively.
Recommended Operating Conditions (Ta = 25C, unless otherwise noted.)
Symbol
Vdd Vdd(I/O) VIH VIL
Parameter
Supply Voltage Supply Voltage(I/O) Digital Input Voltage (High) Digital Input Voltage (Low) Clock Pulse Width (High) Clock Pulse Width (Low) Set-up Time Hold Time
Limits
Min. 3.15 4.75 2.4 0 6.25 6.25 5 5 Typ. 3.30 5.0 Max. 3.45 5.25 Vdd 0.8 -
Unit
V V V V ns ns ns ns
tWH tWL tsu th
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MITSUBISHI Analog ICs
M65533FP
3ch 8-bit 80MHz A/D Converters
Electrical Characteristics (Ta = 25C, AVdd = DVdd = 3.30V, unless otherwise noted.)
(1) Overall Symbol
AIdd(AD R/G/B) DIdd(AD R/G/G) DIdd(I/O R/G/G) DIdd(PLL) DIdd(LO) DIdd(I/O 5)
Parameter
AD(R/G/B) Analog Supply Current AD(R/G/G) Digital Supply Current I/O block Supply Current PLL block Supply Current Logic block Supply Current 5V I/O block Supply Current
Condition
For R/G/B signal For R/G/B signal For R/G/B signal
Limits
Min. Typ. tbf tbf tbf tbf tbf tbf Max.
Unit
mA mA mA mA mA mA
(2) ADC Block Symbol
Res Vdd NL DNL VOH VOL VinA Cin fCLK Vref(+) Vref(M) Vref(-) Rref B.W tpdLH tpdHL tr tf Vclamp
Parameter
Resolution Supply Voltage Integral Nonlinearity Differential Nonlinearity Digital output Voltage "H" Digital output Voltage "L" Analog input range Input Capacitance Max. Conversion Rate Reference Voltgae "High" Reference Voltgae "Middle" Reference Voltgae "Low" Reference Resistor Input Bandwidth Output delay time(L->H) Output delay time(H->L) Output rise time Output fall time Clamp Voltage
Condition
Limits
Min. 3.15 Typ. 8 3.30 Max. 3.45 1.0 1.0 0.7xVdd 0 0.67 80 1.00 10 Vdd 0.3xVdd 1.15
Unit
Bits V LSB LSB V V Vp-p pF MHz
Vref(+)=1.5V, Vref(-)=0.5V Vref(+)=1.5V, Vref(-)=0.5V
Changeable by IIC (16mV step)
1.17 0.84
1.5 1.0 0.5 120
1.65 1.07
V V V Ohms MHz
-3dB input frequency
70 110 110 tbf tbf 160 160
ns ns ns ns
Changeable by IIC (16mV step)
0.25
0.5
0.73
V
(3) PLL Block Symbol
fH fVCO jPLL D.R(PLL)
Parameter
Horizontal frequency VCO frequency maximum jitter PLL Divider Ratio
Condition
Limits
Min. 10 20 Typ. 60 0.5 Max. 100 80 1.0 1376
Unit
KHz MHz ns -
from 800 by 1 step
800
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MITSUBISHI Analog ICs
M65533FP
3ch 8-bit 80MHz A/D Converters
Pin Description -1
Pin No. 31,33,35 5,13,21 44,54,64 66,67 30,32,34 4,12,20 45,55,65 69,70 2,10,18 7,15,23 6,14,22 1,9,17 8,16,24 36 - 43 46 - 53 56 - 63 74 68 29 79 78 80 77 25,26,27 Pin Name DVDDX(A/D) AVDDX(A/D) DVDDX(OUT) VDD(PLL) DGNDX (A/D) AGNDX (A/D) DGNDX(OUT) GND(PLL) XCIN XVRT XVRM XVRB XNB DoX<7:0> FH-IN FILTER CLK-OUT SDA SCL RESET EXT-CLK IN Test<1-3 > O I/O I/O I I I/O O I
I
No connection. It is grounded during actual use. I/O Function Digital Power supply (R/G/B signal) Analog Power supply (R/G/B signal) I/O Power supply (R/G/B signal) PLL Power supply Digital ground (R/G/B signal) Analog ground (R/G/B signal) I/O ground (R/G/B signal) PLL ground R/G/B signal Clamp Input Reference Voltage(+) Input (R/G/B signal) Reference Voltage(M) Input (R/G/B signal) Reference Voltage(-) Input (R/G/B signal) ADC operating current setting BIAS Digital Output (R/G/B signal) H Sync Input PLL filter Clock output IIC Data Input/Output IIC CLK Input Reset signal Input External Clock intput Test terminal
From or To
3.3V 3.3V 3.3V 3.3V GND GND GND GND From LPF Bypass capacitor Bypass capacitor Bypass capacitor Bypass capacitor To Logic LSI
From Sync Sep. LSI (R+C)//C
To Logic LSI From MCU From MCU To Vdd From PLL LSI
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MITSUBISHI Analog ICs
M65533FP
3ch 8-bit 80MHz A/D Converters
Pin Description -2
Pin No. 76 72 73 71 75 28 3,11,19 Pin Name DVDD(I/O 5) DVDD (LO) DGND (I/O 5) DGND (LO) CP-IN DLY-HD out NC
I
No connection. It is grounded during actual use. I/O Function Digital Power supply (5V) Digital Power supply (Logic) Digital ground (5V) Digital ground (Logic) Clamp Pulse Input Delayed HD output
From or To
5V 3.3V GND GND
From Sync Sep. LSI
O
To logic LSI GND or OPEN
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MITSUBISHI Analog ICs
M65533FP
3ch 8-bit 80MHz A/D Converters
Table of Power-down Function( SubAdd=00h, D2-D0)
Digital input code "HHH" "LLL" Power-down function power-down normal operation Default
Setting by IIC BUS
Only Clamp=>"HLL" Only PLL=>"LHL" Only ADC=>"LLH"
Table of CP Function (SubAdd=11h, D0)
CP signal "H" "L" CP function Clamping Hold state CP signal Digital input code D0="H" D0="L"
Setting by IIC BUS
CP Polarity Inversed Not-inversed
Table of Hsync Function(SubAdd=17h, D0)
Digital input code D0="H" D0="L" Hsync function Inversed Not-inversed
Setting by IIC BUS
Default
Table of CLK output Function(SubAdd=13h, D0) Setting by IIC BUS
Digital input code D0="H" D0="L" CLK output function Inversed (180 ) Not-inversed ( 0 ) Default
Table of Internal/External CLK(SubAdd=16h, D5)
Digital input code D5="H" D5="L" CLK output function External Internal Default
Setting by IIC BUS
Table of Digital Output R/G/B < 7 : 0 > Function
Output "HZ" is available at D1="H" of SubAdd=18h
Analog input voltage
7 MSB
Setting by IIC BUS "L"=default
Note
0 LSB
Digital output code
6
1 1
5
1 1
4
1 1
3
1 1
2
1 1
1
1 1
1.500V 1.496V 1.000V 0.996V 0.504V 0.500V
1 1
1 0
1 0
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 0
0 0
0 0
0 0
0 0
0 0
0 0
1 0
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MITSUBISHI Analog ICs
M65533FP
3ch 8-bit 80MHz A/D Converters
Table of Delay adjustment(SubAdd=16h, D3-D0) for External CLK (SubAdd=16h, D5="H")
Digital input code
CLK Delayed Adjustment D3 D2 D1 D0
Setting by IIC BUS
1 1
1 1
1 1
1 0
75ns 70ns 40ns 35ns 5ns 0ns
Default
1 0
0 1
0 1
0 1
0 0
0 0
0 0
1 0
Setting by IIC BUS Table of Vref(+) Voltage adjustment (SubAdd=0Bh, D4-D0:R 0Ch, D4-D0:G 0Dh, D4-D0:B)
Digital input code Vref(+) adjustment Note
D4
1 1
D3
1 1
D2
1 1
D1
1 1
D0
1 0
40LSB 36LSB 0LSB -20LSB -24LSB -80LSB -84LSB
1.5+0.157V
1
0
1
0
1
1.5-0V
Default
1 0
0 1
0 1
0 1
0 1
0 0
0 0
0 0
0 0
1 0
1.5-0.329V
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MITSUBISHI Analog ICs
M65533FP
3ch 8-bit 80MHz A/D Converters Setting by IIC BUS Table of Clamp level adjustment (SubAdd=0Eh, D4-D0:R 0Fh, D4-D0:G 10h, D4-D0:B)
Digital input code
D4 D3 D2 D1 D0
Delay adjustment level
Note
1 1
1 1
1 1
1 1
1 0
60LSB 56LSB 0LSB -4LSB -60LSB -64LSB
0.5V+235mV
1 0
0 1
0 1
0 1
0 1
0.5V-0mV
Default
0 0
0 0
0 0
0 0
1 0
0.5V-251mV Setting by IIC BUS
Table of CLK output Phase (SubAdd=12h, D4 -D0)
Digital input code
D4
1 1
D3
1 1
D2
1 1
D1
1 1
D0
1 0
CLK output phase
1 0
0 1
0 1
0 1
0 1
division into 32 of 1 period
0 0
0 0
0 0
0 0
1 0
0 + 0 * 360/32
Default
Table of CLK output Phase Function (SubAdd=12h,D5)
Digital input code D5="H" D5="L" CLK output Phase Function OFF ON
Setting by IIC BUS
Table of CLK's Pol. for A/D (SubAdd=12h,D6)
Digital input code D6="H" D6="L" CLK's Pol. NEGA POSI
Setting by IIC BUS
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MITSUBISHI Analog ICs
M65533FP
3ch 8-bit 80MHz A/D Converters
Table of PLL divider adjustment (SubAdd=14h,A6-A0 15h,A3-A0)
Digital input code 14h A6 A5 A4 A3 A2 A1 A0 A3 A2 15h A1
Setting by IIC BUS
Divider adjustment
A0
1 1
0 0
1 1
0 0
1 1
1 0
0 1
0 1
0 1
0 1
0 1
fH x 1376 fH x 1375 fH x 1024 fH x 1023 fH x 801 fH x 800
1 0
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 0
1 1
1 1
0 0
0 0
1 1
0 0
0 0
0 0
0 0
1 0
Table of PLL divider adjustment (SubAdd=15h,A6-A5)
Digital input code D6,5="1 1" D6,5="1 0" D6,5="0 1" D6,5="0 0" PLL Pre-divider adjustment
Setting by IIC BUS
1/6 1/4 1/3 1/2
1/2 1/3 1/4 1/6 20 30 40 60 80
O/P Frequency [MHz] 3-0
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MITSUBISHI Analog ICs
M65533FP
3ch 8-bit 80MHz A/D Converters
Table of Reset Function (pin 80)
Reset signal "L" "H" Reset function Reset normal operation
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MITSUBISHI Analog ICs
M65533FP
3ch 8-bit 80MHz A/D Converters
Application Examples
From PC output R-in G-in B-in
LPF & Output Buffer
Input level :0.7Vp-p(typ.) 0.55Vp-p(min.) 0.85Vp-p(max.)
Vdd=3.3V(typ.)&5V(*)
MCU
IIC(**) BUS
M65533FP 3ch 8bit 80MHz A/D Converters PKG:80pinQFP
FH-IN & CP-IN(**)
M52347FP Sync Processor PKG:20P2N
(*) In case of 5VI/F (**) IIC&FH-IN are available for 5VI/F.
Digital Data output < 7:0 > VoH=2.3V(min.), VoL=1.0V(max.)
CLK output VoH=2.3V(min.), VoL=1.0V(max.) To Logic LSI
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MITSUBISHI Analog ICs
M65533FP
3ch 8-bit 80MHz A/D Converters
Analog Input / Digital Output Timing Diagram
sampling timing
XC IN
FH-IN controllable by IIC BUS
CLK(INT)
N Delay cycle = 8 clocks
N+8
DoX<7:0>
N-9
N-8
N-7 tr, tf
N-2
N-1 tpd
N
Notes to the operation 1. Both a ground and a supply planes in a PCB should be as wide as possible for reducing a parasitic inductance and resistance. Especially, for the better performance, the analog plane needs to be much wider. 2. A tantalum or electrolytic capacitor of 10F or more and a ceramic capacitor of 0.01F are tied together, which are connected between a digital supply and ground, also between a analog supply and ground. These capacitors should be placed as close as possible to the IC. They work as bypass capacitors for preventing a degradation in the performance by a supply voltage fluctuation caused by digital signals including a clock and digital inputs and so on. 3. The analog output should be isolated as much as possible from a clock and digital inputs, thus minimizing decoupling and interactive noise.
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MITSUBISHI Analog ICs
M65533FP
3ch 8-bit 80MHz A/D Converters
Application Example (M65533FP)
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MITSUBISHI Analog ICs
M65533FP
3ch 8-bit 80MHz A/D Converters
M65533FP IIC-BUS CONTROL TABLE
(1) Slave address : A6 A5 A4 A3 A2 A1 A0 R/W 10011100 (=9Ch) (2) Salve address format : read S slave address A Sub address A Data Byte A P
Start condition
Acknowledge bit
Stop condition
(3) Sub address byte and Data byte format : read
Block Total No. 1 2 3 4 ADC 5 6 7 8 9 10 CLK /PLL 11 12 13 14 15 Functions Power-down Vref(+) Vol (R) Vref(+) Vol (G) Vref(+) Vol (B) Clamp Vol (R) Clamp Vol (G) Clamp Vol (B) Clamp-in Pol CLK Phase CLKOUT Pol PLL upper
PLL lower & Divider
Bit 3 5 5 5 5 5 5 1 7 1 7 6 5 2 1
Sub Add 00h 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h
Data byte D7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A01 A06 A06 A05 A05 A05 A04 A03 A03 A03 A02 A02 A02 A01 A01 A01 A06 A05 A04 A03 A02 A01 A04 A04 A04 A04 A04 A04 A03 A03 A03 A03 A03 A03 D6 D5 D4 D3 D2 A02 A02 A02 A02 A02 A02 A02 D1 A01 A01 A01 A01 A01 A01 A01 D0 A00 A00 A00 A00 A00 A00 A00 A00 A00 A00 A00 A00 A00 A00
INT/EXT CLK H_Sync Pol ADC Output
(Note) Blanks shoud not be defined. Becuase it may be used for test mode or function check.
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